The present invention relates to integrated circuit devices, and more particularly to integrated circuit output buffers.
Integrated circuits typically include buffer circuits therein for driving on-chip and off-chip loads. Dynamic output control (DOC) can also be provided by output buffers, such as those disclosed in application notes by Texas Instruments, Inc. (see, http://www.ti.com/sc/AVC). In particular, these output buffers having DOC circuitry may provide variable output impedance to reduce signal noise during output transitions. In these buffers, the DOC circuitry is stated as providing enough current to achieve high signaling speeds, while also having the ability to quickly switch the impedance level to reduce the undershoot and overshoot noise that is often found in high-speed logic. Such DOC circuitry may be used advantageously to eliminate the need for damping resistors which can limit noise but typically also increase propagation delay.
Additional buffer circuits are also disclosed in U.S. Pat. No. 5,894,238 to Chien, entitled xe2x80x9cOutput Buffer With Static and Transient Pull-Up and Pull-Down Driversxe2x80x9d. In particular, the ""238 patent discloses an inverting buffer circuit that utilizes a signal fed back from an output node (DOUT) through logic gates to control the transfer of data input signals (OL or /OH) to inputs of a transient driver circuit containing an NMOS pull-down transistor 22 and a PMOS pull-up transistor 12.
Notwithstanding such conventional output buffers with DOC circuitry, however, there still exists a need for output buffers that have excellent noise, propagation delay and impedance matching characteristics.
It is therefore an object of the present invention to provide improved integrated circuit output buffers.
It is another object of the present invention to provide integrated circuit output buffers having low propagation delay.
It is still another object of the present invention to provide integrated circuit output buffers having improved simultaneous-switching noise characteristics.
It is yet another object of the present invention to provide integrated circuit output buffers having reduced supply line-to-output coupling and improved impedance matching characteristics during DC operation.
These and other objects, advantages and features of the present invention may be provided by integrated circuit output buffers having pull-down and pull-up circuits and a control circuit that utilizes a preferred feedback technique that may facilitate a reduction in simultaneous-switching noise during pull-down and pull-up operations and may also improve the impedance matching characteristics of the output buffers during DC conditions. The preferred feedback technique may also limit the degree to which external noise can influence operation of the control circuit. Each of the pull-down and pull-up circuits may be provided by a respective pair of primary and secondary transistors.
In particular, a preferred pull-down circuit is configured so that the primary and secondary pull-down transistors (e.g., NMOS transistors) are electrically coupled to an output signal line (through an ESD protection resistor) and to a first reference signal line (e.g., Vss). The control circuit is designed to activate the pull-down circuit by turning on both the primary and secondary pull-down transistors during a leading portion of the pull-down time interval and by turning off the secondary pull-down transistor during a trailing portion of the pull-down time interval using a first feedback switch that is electrically coupled in series between the output signal line and a gate electrode of the secondary pull-down transistor so that a signal representing a potential of the output signal line can be passed through the first feedback switch to the gate electrode of the secondary pull-down transistor. In contrast, the pull-up circuit is preferably configured so that the primary and secondary pull-up transistors (e.g., PMOS transistors) are electrically coupled to an output signal line and to a second reference signal line (e.g., Vdd). Here, the control circuit is designed to activate the pull-up circuit by turning on both the primary and secondary pull-up transistors during a leading portion of the pull-up time interval and by turning off the secondary pull-up transistor during a trailing portion of the pull-up time interval using a second feedback switch that is electrically coupled in series between the output signal line and a gate electrode of the secondary pull-up transistor.
The control circuit also includes circuitry therein that is responsive to a data input signal (DI) and an output enable signal (OE). The control circuit controls tri-state operation of the output buffer, turns on the first feedback switch when the boolean expression OE{overscore (DI)}=1 (where xe2x80x9cxe2x80x9d represents a boolean AND operation), and turns on the second feedback switch when the boolean expression OEDI=1. The control circuit may also comprise an NMOS pull-down transistor electrically connected in series (source-to-drain) between the gate electrode of the secondary pull-down transistor and the first reference signal line and a PMOS pull-up transistor electrically connected in series between the gate electrode of the secondary pull-up transistor and the second reference signal line. To operate these pull-down and pull-up transistors, the control circuit includes circuitry therein that turns on the NMOS pull-down transistor when the boolean expression OE{overscore (DI)}=0 and turns on the PMOS pull-up transistor when the boolean expression OEDI=0.
According to additional preferred embodiments of the present invention, an integrated circuit output buffer comprises primary and secondary pull-down transistors and an output signal line electrically coupled to a drain of the primary pull-down transistor and a drain of the secondary pull-down transistor. A preferred control circuit is also provided. This control circuit turns on the primary pull-down transistor during first and second consecutive portions of a pull-down time interval and uses a signal fed back from the output signal line to control the timing of when a gate of the secondary pull-down transistor is electrically connected to a drain of the secondary pull-down transistor during the first portion of the pull-down time interval and also control the timing of when the gate electrode of the secondary pull-down transistor is electrically connected to a source of the secondary pull-down transistor during the second portion of the pull-down time interval.
According to these embodiments, a pull-down portion of the control circuit may include a gate pull-up transistor having a drain electrically connected to the drain of the secondary pull-down transistor and a source electrically connected to a gate of the secondary pull-down transistor, and a gate pull-down transistor having a drain electrically connected to the gate of the secondary pull-down transistor and a source electrically connected to a source of the secondary pull-down transistor. These gate pull-up and pull-down transistors can be utilized to selectively turn on the secondary pull-down transistor during a first leading portion of a pull-down time interval and then turn off the secondary pull-down transistor during a second trailing portion of the pull-down time interval. A gate control inverter is also provided having an input electrically coupled to a gate of the gate pull-up transistor and an output electrically coupled to a gate of the gate pull-down transistor. The control circuit also preferably includes a feedback inverter having an input electrically coupled to the output signal line, and a first logic gate (e.g., NOR gate) having a first input electrically coupled to an output of the feedback inverter and an output electrically coupled to the input of the gate control inverter.
In another preferred embodiment, the control circuit is responsive to an input signal (IN) and an output signal (OUT) fed back from the output signal line and includes logic devices therein that provide a gate of the primary pull-down transistor with a first gate signal that tracks {overscore (IN)}, and a gate of at least one of the gate pull-up transistor and the gate pull-down transistor with a second gate signal that is a function of {overscore (IN)}OUT. Alternatively, the control circuit may include logic devices therein that provide a gate of the primary pull-down transistor with a first gate signal that tracks IN, and a gate of at least one of the gate pull-up transistor and the gate pull-down transistor with a second gate signal that is a function of INOUT. Preferably, the second gate signal is provided to the gate of the gate pull-up transistor. The control circuit may also provide the gate of the gate pull-down transistor with a third gate signal that is an inverted version of the second gate signal. The control circuit may also be responsive to an output enable signal (OE) and, if so, the control circuit preferably provides a gate of the primary pull-down transistor with a first gate signal that tracks {overscore (IN)} only when OE is in a first logic state. The second gate signal may also be a function of {overscore (IN)}OUTOE. Related primary and secondary pull-up transistors and control circuitry may also used in the pull-up path to control pull-up of the output signal line in similar manner.